Motorola ColdFire MCF5281 User Manual
Page 316
Fast Ethernet Controller (FEC)
17-6
Freescale Semiconductor
•
Control/status registers
•
Event/statistic counters held in the MIB block
defines the top level memory map.
shows the FEC register memory map.
Table 17-2. Module Memory Map
Address
Function
IPSBAR + 0x1000 – 11FF
Control/Status Registers
IPSBAR + 0x1200 – 12FF
MIB Block Counters
Table 17-3. FEC Register Memory Map
IPSBAR Offset
Register
Width
(bits)
Access
Reset Value
Section/Page
0x1004
Interrupt Event Register (EIR)
32
R/W
0x0000_0000
0x1008
Interrupt Mask Register (EIMR)
32
R/W
0x0000_0000
0x1010
Receive Descriptor Active Register (RDAR)
32
R/W
0x0000_0000
0x1014
Transmit Descriptor Active Register (TDAR)
32
R/W
0x0000_0000
0x1024
Ethernet Control Register (ECR)
32
R/W
0xF000_0000
0x1040
MII Management Frame Register (MMFR)
32
R/W
Undefined
0x1044
MII Speed Control Register (MSCR)
32
R/W
0x0000_0000
0x1064
MIB Control/Status Register (MIBC)
32
R/W
0x0000_0000
0x1084
Receive Control Register (RCR)
32
R/W
0x05EE_0001
0x10C4
Transmit Control Register (TCR)
32
R/W
0x0000_0000
0x10E4
Physical Address Low Register (PALR)
32
R/W
Undefined
0x10E8
Physical Address High Register (PAUR)
32
R/W
See Section
0x10EC
Opcode/Pause Duration (OPD)
32
R/W
See Section
0x1118
Descriptor Individual Upper Address Register (IAUR)
32
R/W
Undefined
0x111C
Descriptor Individual Lower Address Register (IALR)
32
R/W
Undefined
0x1120
Descriptor Group Upper Address Register (GAUR)
32
R/W
Undefined
0x1124
Descriptor Group Lower Address Register (GALR)
32
R/W
Undefined
0x1144
Transmit FIFO Watermark (TFWR)
32
R/W
0x0000_0000
0x114C
FIFO Receive Bound Register (FRBR)
32
R
0x0000_0600
0x1150
FIFO Receive FIFO Start Register (FRSR)
32
R
0x0000_0500
0x1180
Pointer to Receive Descriptor Ring (ERDSR)
32
R/W
Undefined
0x1184
Pointer to Transmit Descriptor Ring (ETDSR)
32
R/W
Undefined
0x1188
Maximum Receive Buffer Size (EMRBR)
32
R/W
Undefined
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3