Motorola ColdFire MCF5281 - Manual (Page 296)

Synchronous DRAM Controller Module
15-24 Freescale Semiconductor
Power-Up Sequence:
move.w #0x0026, d0//Initialize DCR
move.w d0, DCR
move.l #0xFF880300, d0 //Initialize DACR0
move.l d0, DACR0
move.l #0x00740075, d0//Initialize DMR0
move.l d0, DMR0
Precharge Sequence:
move.l #0xFF880308, d0//Set DACR0[IP]
move.l d0, DACR0
move.l #0xBEADDEED, d0//Write and value to memory location to init. precharge
move.l d0, 0xFF880000
Refresh Sequence:
move.l #0xFF888300, d0//Enable refresh bit in DACR0
move.l d0, DACR0
Mode Register Initialization Sequence:
move.l #0x00600075, d0//Mask bit 19 of address
move.l d0, DMR0
move.l #0xFF888340, d0//Enable DACR0[IMRS]; DACR0[RE] remains set
move.l d0, DACR0
move.l #0x00000000, d0//Access SDRAM address to initialize mode register
move.l d0, 0xFF800800
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3