Motorola ColdFire MCF5281 - Manual (Page 58)

ColdFire Core
2-12 Freescale Semiconductor
Figure 2-12. V2 OEP Embedded-Load Part 1
Figure 2-13. V2 OEP Embedded-Load Part 2
For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed
simultaneously allowing single-cycle execution. See
Figure 2-14 where the effective address is of the form
<ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax.
Operand Execution Pipeline
DSOC AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
RGF
Data
Ay
d16
<ea>y
Operand Execution Pipeline
DSOC AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
RGF
Data
Rx
new Rx
<mem>y
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3