Motorola ColdFire MCF5281 - Manual (Page 601)

Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor 28-63
Figure 28-50 shows an active parasitic bipolar NPN transistor when an input signal is subjected to negative
stress conditions. Figure 28-51 shows positive stress conditions can activate a similar PNP transistor.
Figure 28-50. Input Signal Subjected to Negative Stress
Figure 28-51. Input Signal Subjected to Positive Stress
The current into the signal (I
INJN
or I
INJP
) under negative or positive stress is determined by these equations:
Eqn. 28-1
Eqn. 28-2
Where:
V
Stress
= Adjustable voltage source
V
EB
= Parasitic PNP emitter/base voltage
V
BE
= Parasitic NPN base/emitter voltage
R
Stress
= Source impedance (10 k
Ω resistor in
Figure 28-50 and Figure 28-51 on stressed channel)
R
Selected
= Source impedance on channel selected for conversion
The current into (I
In
) the neighboring pin is determined by the K
N
(current coupling ratio) of the parasitic
bipolar transistor (K
N
‹‹ 1). The I
In
can be expressed by this equation:
I
In
= – K
N
* I
INJ
Where:
I
INJ
is either I
INJN
or I
INJP
.
A method for minimizing the impact of stress conditions on the QADC is to strategically allocate QADC
inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions.
Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress
conditions.
R
STRESS
R
SELECTED
Adjacent
10 k Ω
Signal Under
Parasitic
I
injn
I
IN
+
Stress
V
STRESS
Device
Signal V
IN
AN
n
AN
n+1
R
STRESS
R
SELECTED
Adjacent
10 kΩ
Signal Under
Parasitic
I
injP
I
IN
+
Stress
V
STRESS
Device
Signal
V
IN
V
DDA
AN
n
AN
n+1
I
INJN
V
Stress
V
BE
–
( )
–
R
Stress
----------------------------------------------- =
I
INJP
V
Stress
V
EB
– V
DDA
–
R
Stress
--------------------------------------------------------------- =
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3