Motorola ColdFire MCF5281 - Manual (Page 758)

Index-10 Freescale Semiconductor
model 22-11
receive 22-11
transmit 22-12
registers
address (QAR) 22-7
command RAM (QCRn) 22-8
data (QDR) 22-8
delay (QDLYR) 22-5
interrupt (QIR) 22-6
mode (QMR) 22-3
wrap (QWR) 22-6
Rx
RAM 22-11
signals 22-2
timing diagram 33-25
Tx
delays 22-13
length 22-14
RAM 22-12
R
Registers
cache
access control 0–1 (ACRn) 2-7 , 4-6
control (CACR) 2-7 , 4-3
chip configuration module
chip configuration (CCR) 27-4
chip identification (CIR) 27-6
reset configuration (RCON) 27-5
chip select module
address (CSARn) 12-6
control (CSCRn) 12-7
mask (CSMRn) 12-6
clock module
synthesizer control (SYNCR) 9-6
synthesizer status (SYNSR) 9-8
ColdFire Flash module
clock divider (CFMCLKD) 6-9
command (CFMCMD) 6-16
configuration (CFMCR) 6-8
data access (CFMDACC) 6-14
FLASHBAR 6-5
protection (CFMPROT) 6-12
security (CFMSEC) 6-10
supervisor access (CFMSACC) 6-13
user status (CFMUSTAT) 6-15
core
address (An) 2-4
condition code (CCR) 2-6
data (Dn) 2-4
program counter (PC) 2-7
stack pointer (A7) 2-5
status register (SR) 2-8
vector base (VBR) 2-7
debug
address attribute trigger (AATR) 30-7
address breakpoint (ABLR, ABHR) 30-9
configuration/status (CSR) 30-10
data breakpoint/mask (DBR, DBMR) 30-12
program counter breakpoint/mask (PBR/PBMR) 30-13
trigger definition (TDR) 30-14
DMA controller
byte count (BCRn) 16-7
control (DCRn) 16-7
destination address (DARn) 16-6
request control (DMAREQC) 16-2
source address (SARn) 16-5
status (DSRn) 16-10
EMAC
mask (MASK) 3-5
status (MACSR) 3-3
EPORT
data direction (EPDDR) 11-4
flag (EPFR) 11-6
pin assignment (EPPAR) 11-3
pin data (EPPDR) 11-6
port data (EPDR) 11-5
port interrupt enable (EPIER) 11-5
Ethernet
control (ECR) 17-12
descriptor group upper/lower address
(GAUR/GALR) 17-21
descriptor individual upper/lower (IAUR/IALR) 17-20
descriptor individual upper/lower address
(IAUR/IALR) 17-20
FIFO receive bound (FRBR) 17-22
FIFO receive start (FRSR) 17-23
FIFO transmit FIFO watermark (TFWR) 17-22
interrupt event (EIR) 17-9
interrupt mask (EIMR) 17-10
MIB control (MIBC) 17-16
MII management frame (MMFR) 17-13
MII speed control (MSCR) 17-15
opcode/pause duration (OPD) 17-19
physical address low (PALRn) 17-18
physical address low/high (PALR, PAUR) 17-18
receive buffer size (EMRBR) 17-24
receive control (RCR) 17-16
receive descriptor active (RDAR) 17-11
receive descriptor ring start (ERDSR) 17-23
transmit buffer descriptor ring start (ETSDR) 17-24
transmit control (TCR) 17-17
transmit descriptor active (TDAR) 17-12
FlexCAN
control 0–2 (CANCTRLn) 25-20 – 25-22
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3