Motorola ColdFire MCF5281 - Manual (Page 655)

Debug Support
Freescale Semiconductor 30-37
30.6 Real-Time Debug Support
The ColdFire Family provides support debugging real-time applications. For these types of embedded
systems, the processor must continue to operate during debug. The foundation of this area of debug support
is that while the processor cannot be halted to allow debugging, the system can generally tolerate small
intrusions into the real-time operation.
The debug module provides three types of breakpoints—PC with mask, operand address range, and data
with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger
response also programmable. The debug module programming model can be written from either the
external development system using the debug serial interface or from the processor’s supervisor
programming model using the WDEBUG instruction. Only CSR is readable using the external
development system.
30.6.1 Theory of Operation
Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is
programmed into TDR. As shown in
Table 30-21 , when a breakpoint is triggered, an indication
(CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status,
operands, or branch addresses.
The breakpoint status is also posted in the CSR. Note that CSR[BSTAT] is cleared by a CSR read when
either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not
enabled. Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates,
a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before
the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local
bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these
interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a
breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher
than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the
processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur before the targeted instruction executes. This is possible because the PC breakpoint is
Table 30-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
DDATA[3:0]/CSR[BSTAT]
1
1
Encodings not shown are reserved for future use.
Breakpoint Status
0000/0000 No breakpoints enabled
0010/0001 Waiting for level-1 breakpoint
0100/0010 Level-1 breakpoint triggered
1010/0101 Waiting for level-2 breakpoint
1100/0110 Level-2 breakpoint triggered
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3