Motorola ColdFire MCF5281 - Manual (Page 562)

Queued Analog-to-Digital Converter (QADC)
28-24 Freescale Semiconductor
28.6.7 Conversion Command Word Table (CCW)
The CCW table is 64 half-word (128 byte) long RAM with 10 bits of each entry implemented. The CCW
table is written by the user and is not modified by the QADC. Each CCW requests the conversion of one
analog channel to a digital result. The CCW specifies the analog channel number, the input sample time,
and whether the queue is to pause after the current CCW. The bits in this register are read anytime (except
during stop mode), write anytime (except during stop mode).
7 6 5 4 3 2 1 0
Field — CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20
Reset 0011_1111
R/W: R
Address IPSBAR + 0x19_0012, 0x19_0013
Figure 28-13. QADC Status Register 1 (QASR1)
Table 28-13. QASR1 Field Descriptions
Bit(s) Name Description
15–14 — Reserved, should be cleared.
13–8 CWPQ1 Queue 1 command word pointer. Points to the last queue 1 CCW executed. This is a
read-only field with a valid range of 0 to 63; writes have no effect. CWPQ1 always
points to the last executed CCW in queue 1, regardless of which queue is active.
In contrast to CWP, CPWQ1 is updated when a conversion result is written. When the
QADC finishes a conversion in queue 1, both the result register is written and CWPQ1
is updated.
When queue 1 operation is terminated after a CCW is read that is pointed to by BQ2,
CWP points to BQ2 while CWPQ1 points to the last queue 1 CCW.
During stop mode, CWPQ1 is reset to 63, because the control registers and the
analog logic are reset. When debug mode is entered, CWPQ1 is not changed; it points
to the last executed CCW in queue 1.
7–6 — Reserved, should be cleared.
5–0 CWPQ Queue 2 command word pointer. Points to the last queue 2 CCW executed. This is a
read-only field with a valid range of 0 to 63; writes have no effect. CWPQ2 always
points to the last executed CCW in queue 2, regardless which queue is active.
In contrast to CWP, CPWQ2 is updated when a conversion result is written. When the
QADC finishes a conversion in queue 2, both the result register is written and CWPQ2
is updated.
During stop mode, CWPQ2 is reset to 63 because the control registers and the analog
logic are reset. When debug mode is entered, CWPQ2 is not changed; it points to the
last executed CCW in queue 2.
15 10 9 8
Field — P BYP
Reset 0000_00 Unaffected
R/W: R R/W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3