Motorola ColdFire MCF5281 User Manual
Page 70
ColdFire Core
2-24
Freescale Semiconductor
Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
11–8
Reserved.
7–4
ISA
ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (This is the value used for this device.)
Else Reserved
3–0
DEBUG
Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+
1011 DEBUG_D+
1111 DEBUG_D+PST Buffer
Else Reserved
BDM: Load: 0x1 (D1)
Store: 0x1 (D1)
Access: User read-only
BDM read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CLSZ
CCAS
CCSZ
FLASHSZ
0
0
0
W
Reset
0
0
0
1
0
0
1
1
1
0
1
1
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
MBSZ
UCAS
0
0
0
0
SRAMSZ
0
0
0
W
Reset
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
Figure 2-19. D1 Hardware Configuration Info
Table 2-10. D1 Hardware Configuration Information Field Description
Field
Description
31–30
CLSZ
Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
29–28
CCAS
Configurable cache associativity.
00
Four-way
01
Direct mapped (This is the value used for this device)
Else Reserved for future use
Table 2-9. D0 Hardware Configuration Info Field Description (continued)
Field
Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3