19 transmit fifo watermark register (tfwr), 20 fifo receive bound register (frbr) – Motorola ColdFire MCF5281 User Manual
Page 332
Fast Ethernet Controller (FEC)
17-22
Freescale Semiconductor
17.4.19 Transmit FIFO Watermark Register (TFWR)
The TFWR controls the amount of data required in the transmit FIFO before transmission of a frame can
begin. This allows you to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value
minimizes the risk of transmit FIFO underrun due to contention for the system bus. The byte counts
associated with the TFWR field may need to be modified to match a given system requirement (worst case
bus access latency by the transmit data DMA channel).
17.4.20 FIFO Receive Bound Register (FRBR)
FRBR indicates the upper address bound of the FIFO RAM. Drivers can use this value, along with the
FRSR, to appropriately divide the available FIFO RAM between the transmit and receive data paths.
Table 17-22. GALR Field Descriptions
Field
Description
31–0
GADDR2
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains
hash index bit 0.
IPSBAR
Offset:
0x1144
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TFWR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
Figure 17-19. Transmit FIFO Watermark Register (TFWR)
Table 17-23. TFWR Field Descriptions
Field
Description
31–2
Reserved, must be cleared.
1–0
TFWR
Number of bytes written to transmit FIFO before transmission of a frame begins
00 64 bytes written
01 64 bytes written
10 128 bytes written
11 192 bytes written
IPSBAR
Offset:
0x114C
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R_BOUND
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
0
0
Figure 17-20. FIFO Receive Bound Register (FRBR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3