Motorola ColdFire MCF5281 - Manual (Page 578)

Queued Analog-to-Digital Converter (QADC)
28-40 Freescale Semiconductor
Figure 28-27. CCW Priority Situation 5
The remaining situations, S6 through S11, show the impact of a queue 1 trigger event occurring during
queue 2 execution. Because queue 1 has higher priority, the conversion taking place in queue 2 is aborted
so that there is no variable latency time in responding to queue 1 trigger events.
In situation 6 ( Figure 28-28 ), the conversion initiated by the second CCW in queue 2 is aborted just before
the conversion is complete, so that queue 1 execution can begin. Queue 2 is considered suspended. After
queue 1 is finished, queue 2 starts over with the first CCW, when the RESUME control bit is set to 0.
Situation S7 (
Figure 28-29 ) shows that when pause operation is not used with queue 2, queue 2 suspension
works the same way.
Figure 28-28. CCW Priority Situation 6
Q1:
Q2:
QS:
IDLE
IDLE IDLE
0000 1000 0010
ACTIVE
0000
C1 C2
T1
Q1:
C1 C2
PF2
C3 C4
C3 C4
CF2
IDLE
1011
TRIG
Q2:
T2 T2
PF1
PAUSE
ACTIVE PAUSE
TOR2
T2 T2
CF1
TOR2
T1
ACTIVE
TRIG
0110
ACTIVE
ACTIVE
0101 1001 1011
IDLE
Q1:
Q2:
QS
IDLE
IDLE
0000 1000
ACTIVE
C1 C2
T1
Q1:
C1
C3 C4
IDLE
Q2:
PF1
PAUSE
ACTIVE
CF1
T1
ACTIVE
SUSPEND
0100
ACTIVE
ACTIVE
0110 1010
C1 C2 C3 C4
CF2
T2
0010 0000
RESUME = 0
C2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3