2 program, erase, and verify sequences, 2 program, erase, and verify sequences -18, Warning – Motorola ColdFire MCF5281 User Manual

Page 130

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ColdFire Flash Module (CFM)

6-18

Freescale Semiconductor

Consider the following example for f

SYS

= 66 MHz:

So, for f

SYS

= 66 MHz, writing 0x54 to CFMCLKD will set f

CLK

to 196.43 kHz which is a valid frequency

for the timing of program and erase operations.

WARNING

For proper program and erase operations, it is critical to set f

CLK

between

150 kHz and 200 kHz. Array damage due to overstress can occur when f

CLK

is less than 150 kHz. Incomplete programming and erasure can occur when
f

CLK

is greater than 200 kHz.

NOTE

Command execution time increases proportionally with the period of f

CLK

.

When CFMCLKD is written, the DIVLD bit is set automatically. If DIVLD is 0, CFMCLKD has not been
written since the last reset. Program and erase commands will not execute if this register has not been
written (see

Section 6.4.3.4, “Flash User Mode Illegal Operations

”).

6.4.3.2

Program, Erase, and Verify Sequences

A command state machine is used to supervise the write sequencing of program, erase, and verify
commands. To prepare for a command, the CFMUSTAT[CBEIF] flag should be tested to ensure that the
address, data, and command buffers are empty. If CBEIF is set, the command write sequence can be
started.

This three-step command write sequence must be strictly followed. No intermediate writes to the CFM
module are permitted between these three steps. The command write sequence is:

1. Write the 32-bit longword to be programmed to its location in the CFM array. The address and data

will be stored in internal buffers. All address bits are valid for program commands. The value of
the data written for verify and erase commands is ignored. For mass erase or verify, the address can
be any location in the CFM array. For page erase, address bits [9:0] are ignored.

f

SYS

2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))

f

CLK

=

f

SYS

2 x 200kHz x (1 + (PRDIV8 x 7))

DIV[5:0] =

66 MHz

400 kHz x (1 + (1 x 7))

=

= 20

f

SYS

2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))

f

CLK

=

66 MHz

2 x (20 + 1) x (1 + (1 x 7))

=

= 196.43 kHz

MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

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