Motorola ColdFire MCF5281 - Manual (Page 549)

Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor 28-11
11–7 — Reserved, should be cleared.
6–0 QPR Prescaler clock divider. Selects the system clock divisor to generate the QADC clock
as
Table 28-5 shows. The resulting QADC clock rate can be given as:
where:
1
≤
QPR[6:0]
≤
127.
If QPR[6:0] = 0, then the QPR register field value is read as a 1 and the prescaler
divisor is 2.
The prescaler should be selected so that the QADC clock rate is within the required
f
QCLK
range. See Chapter 33, “Electrical Characteristics” .
Table 28-5. Prescaler f
SYS
Divide-by Values
QPR[6:0]
f
SYS
Divisor
QPR[6:0]
f
SYS
Divisor
QPR[6:0]
f
SYS
Divisor
QPR[6:0]
f
SYS
Divisor
0000000 4 0100000 66 1000000 130 1100000 194
0000001 4 0100001 68 1000001 132 1100001 196
0000010 6 0100010 70 1000010 134 1100010 198
0000011 8 0100011 72 1000011 136 1100011 200
0000100 10 0100100 74 1000100 138 1100100 202
0000101 12 0100101 76 1000101 140 1100101 204
0000110 14 0100110 78 1000110 142 1100110 206
0000111 16 0100111 80 1000111 144 1100111 208
0001000 18 0101000 82 1001000 146 1101000 210
0001001 20 0101001 84 1001001 148 1101001 212
0001010 22 0101010 86 1001010 150 1101010 214
0001011 24 0101011 88 1001011 152 1101011 216
0001100 26 0101100 90 1001100 154 1101100 218
0001101 28 0101101 92 1001101 156 1101101 220
0001110 30 0101110 94 1001110 158 1101110 222
0001111 32 0101111 96 1001111 160 1101111 224
0010000 34 0110000 98 1010000 162 1110000 226
0010001 36 0110001 100 1010001 164 1110001 228
0010010 38 0110010 102 1010010 166 1110010 230
0010011 40 0110011 104 1010011 168 1110011 232
0010100 42 0110100 106 1010100 170 1110100 234
Table 28-4. QACR0 Field Descriptions (continued)
Bit(s) Name Description
f
QCLK
=
f
SYS
2(QPR[6:0] + 1)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3