Chapter 5 static ram (sram), 1 sram features, 2 sram operation – Motorola ColdFire MCF5281 User Manual
Page 109: 3 sram programming model, 1 sram base address register (rambar), Chapter 5, Static ram (sram), Sram features -1, Sram operation -1, Sram programming model -1
Freescale Semiconductor
5-1
Chapter 5
Static RAM (SRAM)
5.1
SRAM Features
•
One 64-Kbyte SRAM
•
Single-cycle access
•
Physically located on processor's high-speed local bus
•
Memory location programmable on any 0-modulo-64 Kbyte address
•
Byte, word, longword address capabilities
5.2
SRAM Operation
The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a
single cycle. The location of the memory block can be specified to any 0-modulo-64K address within the
4-GByte address space. The memory is ideal for storing critical code or data structures or for use as the
system stack. Because the SRAM module is physically connected to the processor's high-speed local bus,
it can service processor-initiated access or memory-referencing commands from the debug module.
Depending on configuration information, instruction fetches may be sent to both the cache and the SRAM
block simultaneously. If the reference is mapped into the region defined by the SRAM, the SRAM
provides the data back to the processor, and the cache data discarded. Accesses from the SRAM module
are not cached.
The SRAM is dual-ported to provide DMA access. The SRAM is partitioned into two physical memory
arrays to allow simultaneous access to both arrays by the processor core and another bus master. See
Chapter 8, “System Control Module (SCM)
” for more information.
5.3
SRAM Programming Model
The SRAM programming model includes a description of the SRAM base address register (RAMBAR),
SRAM initialization, and power management.
5.3.1
SRAM Base Address Register (RAMBAR)
The configuration information in the SRAM base address register (RAMBAR) controls the operation of
the SRAM module.
•
The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only
access to this register.
•
The RAMBAR can be read or written from the debug module in a similar manner.
•
All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR, and return zeroes when read from the debug module.
•
The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are
unaffected.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3