Motorola ColdFire MCF5281 - Manual (Page 142)

Power Management
7-6 Freescale Semiconductor
7.3.1.2 Wait Mode
Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is
detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts,
which cause the CPU to exit from wait mode.
7.3.1.3 Doze Mode
Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines
individual operational characteristics in doze mode. Peripherals which continue to run and have the
capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.
Peripherals which are stopped will restart operation on exit from doze mode as defined for each peripheral.
7.3.1.4 Stop Mode
Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the
system are stopped and the peripherals cease operation.
Stop mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.
The following subsections specify the operation of each module while in and when exiting low-power
modes.
NOTE
Entering stop mode will disable the SDRAMC including the refresh counter.
If SDRAM is used, then code is required to insure proper entry and exit from
stop mode. See
Section 7.3.2.5, “SDRAM Controller (SDRAMC) ” for more
information.
7.3.1.5 Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation and remain in a
static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description
for further details). A peripheral may be disabled at any time and will remain disabled during any
low-power mode of operation.
7.3.2 Peripheral Behavior in Low-Power Modes
7.3.2.1 ColdFire Core
The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
7.3.2.2 Static Random-Access Memory (SRAM)
SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power
mode.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3