Motorola ColdFire MCF5281 - Manual (Page 181)

Clock Module
Freescale Semiconductor 9-11
CAUTION
XTAL must be tied low in external clock mode when reset is asserted. If it
is not, clocks could be suspended indefinitely.
The external clock is divided by two internally to produce the system clocks.
9.7.2 Clock Operation During Reset
In external clock mode, the system is static and does not recognize reset until a clock is applied to EXTAL.
In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock
to the PLL begins operating within the limits given in the electrical specifications.
If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system clock
source changes to the PLL operating in SCM. If SCM is not functional, the system becomes static.
Alternately, if the LOCEN bit in SYNCR is cleared when the PLL fails, the system becomes static. If
external reset is asserted, the system cannot enter reset unless the PLL is capable of operating in SCM.
9.7.3 System Clock Generation
In normal PLL clock mode, the default system frequency is two times the reference frequency after reset.
The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency multiplier.
When programming the PLL, do not exceed the maximum system clock frequency listed in the electrical
specifications. Use this procedure to accommodate the frequency overshoot that occurs when the MFD bits
are changed:
1. Determine the appropriate value for the MFD and RFD fields in the SYNCR. The amount of jitter
in the system clocks can be minimized by selecting the maximum MFD factor that can be paired
with an RFD factor to provide the required frequency.
2. Write a value of RFD (from step 1) + 1 to the RFD field of the SYNCR.
3. Write the MFD value from step 1 to the SYNCR.
4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step
1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required
frequency.
NOTE
Keep the maximum system clock frequency below the limit given in the
Electrical Characteristics.
9.7.4 PLL Operation
In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock frequency
by 2x to 9x, provided that the system clock frequency remains within the range listed in electrical
specifications. For example, if the reference frequency is 2 MHz, the PLL can synthesize frequencies of 4
MHz to 18 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the PLL.
1
f
ref
= input reference frequency
f
sys
= CLKOUT frequency
MFD ranges from 0 to 7.
RFD ranges from 0 to 7.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3