Motorola ColdFire MCF5281 - Manual (Page 199)

Interrupt Controller Modules
Freescale Semiconductor 10-9
NOTE
If an interrupt source is being masked in the interrupt controller mask
register (IMR) or a module’s interrupt mask register while the interrupt
mask in the status register (SR[I]) is set to a value lower than the interrupt’s
level, a spurious interrupt may occur. This is because by the time the status
register acknowledges this interrupt, the interrupt has been masked. A
spurious interrupt is generated because the CPU cannot determine the
interrupt source. To avoid this situation for interrupts sources with levels
1-6, first write a higher level interrupt mask to the status register, before
setting the mask in the IMR or the module’s interrupt mask register. After
the mask is set, return the interrupt mask in the status register to its previous
value. Since level seven interrupts cannot be disabled in the status register
prior to masking, use of the IMR or module interrupt mask registers to
disable level seven interrupts is not recommended.
10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism to allow
software generation of interrupts for each possible source for functional or debug purposes. The system
design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or
more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRCn register. The
assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register.
The INTFRCn register is cleared by reset.
Table 10-7. IMRLn Field Descriptions
Bits Name Description
31–1 INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding
IMRLn bit determines whether an interrupt condition can generate an interrupt.
The corresponding IPRLn bit reflects the state of the interrupt signal even if the
corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
0 MASKALL Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and
IMRLn to ones, disabling all interrupt sources, and providing a global mask-all
capability.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3