2 ethernet interrupt event register (eir), 2 ethernet interrupt event register (eir) -9 – Motorola ColdFire MCF5281 User Manual
Page 319
Fast Ethernet Controller (FEC)
Freescale Semiconductor
17-9
17.4.2
Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the interrupt
mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect. This register
is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and
internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB,
and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,
BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters:
•
HBERR - IEEE_T_SQE
•
BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
•
BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
•
LATE_COL - IEEE_T_LCOL
•
COL_RETRY_LIM - IEEE_T_EXCOL
•
XFIFO_UN - IEEE_T_MACERR
Software may choose to mask off these interrupts because these errors are visible to network management
via the MIB counters.
0x12DC
Flow control pause frames received (IEEE_R_FDXFC)
0x12E0
Octet count for frames received without error (IEEE_R_OCTETS_OK)
IPSBAR
Offset:
0x1004
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
HB
ERR
BABR BABT GRA
TXF
TXB
RXF
RXB
MII
EB
ERR
LC
RL
UN
0
0
0
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-2. Ethernet Interrupt Event
Register (EIR)
Table 17-4. MIB Counters Memory Map (continued)
IPSBAR Offset
Register
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3