Motorola ColdFire MCF5281 - Manual (Page 345)

Fast Ethernet Controller (FEC)
Freescale Semiconductor 17-35
17.5.8 FEC Frame Reception
The FEC receiver works with almost no intervention from the host and can perform address recognition,
CRC checking, short frame checking, and maximum frame length checking. The Ethernet controller
receives serial data lsb first.
When the driver enables the FEC receiver by setting ECR[ETHER_EN], it immediately starts processing
receive frames. When FEC_RXDV is asserted, the receiver first checks for a valid PA/SFD header. If the
PA/SFD is valid, it is stripped and the receiver processes the frame. If a valid PA/SFD is not found, the
frame is ignored.
In serial mode, the first 16 bit times of RX_D0 following assertion of FEC_RXDV are ignored. Following
the first 16 bit times, the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is
detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data
sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected,
the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame are received, the FEC performs address recognition on the frame.
After a collision window (64 bytes) of data is received and if address recognition has not rejected the
frame, the receive FIFO signals the frame is accepted and may be passed on to the DMA. If the frame is a
runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to reject the frame.
Therefore, no collision fragments are presented to you except late collisions, which indicate serious LAN
problems.
During reception, the Ethernet controller checks for various error conditions and after the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, CR, OV, and TR status bits, and the frame length. See
Section 17.5.15.2, “Reception
Errors,” for more details.
Receive buffer (RXB) and frame interrupts (RFINT) may be generated if enabled by the EIMR register. A
receive error interrupt is a babbling receiver error (BABR). Receive frames are not truncated if they exceed
the max frame length (MAX_FL); however, the BABR interrupt occurs and the LG bit in the receive buffer
descriptor (RxBD) is set. See
Section 17.5.1.2, “Ethernet Receive Buffer Descriptor (RxBD),” for more
details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits
into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT
bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame is received and is in memory. The
Ethernet controller then waits for a new frame.
17.5.9 Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual (unicast), group
(multicast), or broadcast (all-ones group address). The difference between an individual address and a
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3