Motorola ColdFire MCF5281 - Manual (Page 356)

Watchdog Timer Module
18-2 Freescale Semiconductor
18.3 Block Diagram
Figure 18-1. Watchdog Timer Block Diagram
18.4 Signals
The watchdog timer module has no off-chip signals.
18.5 Memory Map and Registers
This subsection describes the memory map and registers for the watchdog timer. The watchdog timer has
a IPSBAR offset for base address of 0x0014_0000.
18.5.1 Memory Map
Refer to Table 18-2 for an overview of the watchdog memory map.
16-bit WMR
16-bit Watchdog Counter
Count = 0
System Divide by
Reset Clock
IPBUS
8192
16-bit WCNTR 16-bit WSR
IPBUS
Load Counter
EN
WAIT
DOZE
HALTED
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3