Motorola ColdFire MCF5281 - Manual (Page 397)

DMA Timers (DTIM0–DTIM3)
Freescale Semiconductor 21-5
21.2.2 DMA Timer Extended Mode Registers (DTXMRn)
The DTXMRn registers program DMA request and increment modes for the timers.
21.2.3 DMA Timer Event Registers (DTERn)
DTERn, shown in Figure 21-4 , reports capture or reference events by setting DTERn[CAP] or
DTERn[REF]. This reporting happens regardless of the corresponding DMA request or interrupt enable
values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value); both bits can
be cleared at the same time. If configured to generate an interrupt request, clear REF and CAP early in the
interrupt service routine so the timer module can negate the interrupt request signal to the interrupt
controller. If configured to generate a DMA request, processing of the DMA data transfer automatically
clears the REF and CAP flags via the internal DMA ACK signal.
IPSBAR
Offset:
0x00_0402 (DTXMR0)
0x00_0442 (DTXMR1)
0x00_0482 (DTXMR2)
0x00_04C2 (DTXMR3) Access: User read/write
7 6 5 4 3 2 1 0
R
DMAEN
0 0 0 0 0 0
MODE16
W
Reset: 0 0 0 0 0 0 0 0
Figure 21-3. DTXMRn Registers
Table 21-3. DTXMRn Field Descriptions
Field Description
7
DMAEN
DMA request. Enables DMA request output on counter reference match or capture edge event.
0 DMA request disabled
1 DMA request enabled
6–1 Reserved, must be cleared.
0
MODE16
Selects the increment mode for the timer. Setting MODE16 is intended to exercise the upper bits of the 32-bit timer
in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s
upper 16 bits mirror its lower 16 bits. All 32 bits of the counter remain compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3