Motorola ColdFire MCF5281 - Manual (Page 410)

Queued Serial Peripheral Interface (QSPI)
22-6 Freescale Semiconductor
22.3.3 QSPI Wrap Register (QWR)
The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations.
22.3.4 QSPI Interrupt Register (QIR)
The QIR contains QSPI interrupt enables and status flags.
IPSBAR
Offset:
0x00_0348 (QWR) Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HALT WREN WRTO CSIV ENDQP
CPTQP
NEWQP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-5. QSPI Wrap Register (QWR)
Table 22-5. QWR Field Descriptions
Field Description
15
HALT
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands after it has completed execution
of the current command.
14
WREN
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by
QWR[NEWQP] and continue execution.
13
WRTO
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
12
CSIV
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during
a transfer (that is, inactive state is 0, chip selects are active high).
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during
a transfer (that is, inactive state is 1, chip selects are active low).
11–8
ENDQP
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
7–4
CPTQP
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed.
This field is read only.
3–0
NEWQP
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.
IPSBAR
Offset:
0x00_034C (QIR) Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WCEFB ABRTB
0
ABRTL WCEFE ABRTE
0
SPIFE
0 0 0 0 WCEF ABRT 0 SPIF
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-6. QSPI Interrupt Register (QIR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3