Motorola ColdFire MCF5281 - Manual (Page 482)

FlexCAN
25-12 Freescale Semiconductor
A received remote frame is not stored in a receive message buffer. It is only used to trigger the automatic
transmission of a frame in response. The mask registers are not used in remote frame ID matching. All ID
bits (except RTR) of the incoming received frame must match for the remote frame to trigger a response
transmission.
25.4.5 Overload Frames
Overload frame transmissions are not initiated by the FlexCAN unless certain conditions are detected on
the CAN bus. These conditions include:
• Detection of a dominant bit in the first or second bit of intermission.
• Detection of a dominant bit in the seventh (last) bit of the end-of-frame (EOF) field in receive
frames.
• Detection of a dominant bit in the eighth (last) bit of the error frame delimiter or overload frame
delimiter.
25.4.6 Time Stamp
The value of the free-running 16-bit timer is sampled at the beginning of the identifier field on the CAN
bus. For a message being received, the time stamp will be stored in the time stamp entry of the receive
message buffer at the time the message is written into that buffer. For a message being transmitted, the time
stamp entry will be written into the transmit message buffer once the transmission has completed
successfully.
The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This
feature allows network time synchronization to be performed.
25.4.7 Listen-Only Mode
In listen-only mode, the FlexCAN module is able to receive messages without giving an acknowledgment.
Whenever the module enters this mode the status of the Error Counters is frozen and the FlexCAN module
operates like in error passive mode. Since the module does not influence the CAN bus in this mode the
host device is capable of functioning like a monitor or for automatic bit-rate detection.
25.4.8 Bit Timing
The FlexCAN module uses three 8-bit registers to set up the bit timing parameters required by the CAN
protocol. Control registers 1 and 2 (CANCTRL1, CANCTRL2) contain the PROPSEG, PSEG1, PSEG2,
and the RJW fields which allow the user to configure the bit timing parameters. The prescaler divide
register (PRESDIV) allows the user to select the ratio used to derive the S-clock from the system clock.
The time quanta clock operates at the S-clock frequency.
Table 25-7 provides examples of system clock,
CAN bit rate, and S-clock bit timing parameters.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3