Motorola ColdFire MCF5281 - Manual (Page 497)

FlexCAN
Freescale Semiconductor 25-27
25.5.9 Interrupt Mask Register (IMASK)
IMASK contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer will
generate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAG bit
is set).
8 RXWARN Receiver error status flag. The RXWARN status flag reflects the status of the FlexCAN
receive error counter.
0 Receive error counter
<
96.
1 Receive error counter
≥
96.
7 IDLE Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 The CAN bus is not idle.
1 The CAN bus is idle.
6 TX/RX Transmit/receive status. The TX/RX bit indicates when the FlexCAN module is transmitting
or receiving a message. TX/RX has no meaning when IDLE = 1.
0 The FlexCAN is receiving a message if IDLE = 0.
1 The FlexCAN is transmitting a message if IDLE = 0.
5–4 FCS Fault confinement state. The FCS[1:0] field describes the state of the FlexCAN. If the
SOFTRST bit in CANMCR is asserted while the FlexCAN is in the bus off state, the error and
status register is reset, including FCS[1:0]. However, as soon as the FlexCAN exits reset,
FCS[1:0] bits will again reflect the bus off state. Refer to
Section 25.5.11, “FlexCAN Receive
Error Counter (RXECTR) ” for more information on entry into and exit from the various fault
confinement states.
00 Error active
01 Error passive
1X Reserved
3 — Reserved, should be cleared.
2 BOFFINT Bus off interrupt. The BOFFINT bit is used to request an interrupt when the FlexCAN enters
the bus off state. To clear this bit, first read it as a one, then write a one. Writing zero has no
effect.
0 No bus off interrupt requested.
1 When the FlexCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in
CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after
reset.
1 ERRINT Error interrupt. The ERRINT bit is used to request an interrupt when the FlexCAN detects a
transmit or receive error.
To clear this bit, first read it as a one, then write a one. Writing zero
has no effect.
0 No error interrupt request.
1 If an event which causes one of the error bits in the error and status register to be set
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
0 WAKEINT Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
FlexCAN module is in low-power stop mode. To clear this bit, first read it as a one, then write
a one. Writing zero has no effect.
0 No wake interrupt requested.
1 When the FlexCAN is in low-power stop mode and a recessive to dominant transition is
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an
interrupt request is generated.
Table 25-17. ESTAT Field Descriptions (continued)
Bits Name Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3