Ut. see, Section 28.6.4, “port qa and qb data, Direction register (ddrqa & ddrqb) – Motorola ColdFire MCF5281 User Manual
Page 547
Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor
28-9
Note: The reset value for these fields is the current signal state if DDR is an input; otherwise, they are undefined.
28.6.4
Port QA and QB Data Direction Register (DDRQA & DDRQB)
DDRQA and DDRQB are associated with port QA and QB digital I/O signals. Setting a bit in these
registers configures the corresponding signal as an output. Clearing a bit in these registers configures the
corresponding signal as an input. During QADC initialization, port QA and QB signals that will be used
as direct or multiplexed analog inputs must have their corresponding data direction register bits cleared.
When a port QA or QB signal that is programmed as an output is selected for analog conversion, the
voltage sampled is that of the output digital driver as influenced by the load.
When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are
ignored for the bits corresponding to PQA[1:0], and the two multiplexed address (MA[1:0]) output signals.
The MA[1:0] signals are forced to be digital outputs, regardless of their data direction setting, and the
multiplexed address outputs are driven. The data returned during a port data register read is the value of
the MA[1:0] signals, regardless of their data direction setting.
Similarly, when the external trigger signals are assigned to port signals and external trigger queue
operating mode is selected, the data direction setting for the corresponding signals, PQA3 and/or PQA4,
is ignored. The port signals are forced to be digital inputs for ETRIG1 and/or ETRIG2. The data returned
during a port data register read is the value of the ETRIG[2:1] signals, regardless of their data direction
setting.
NOTE
Use caution when mixing digital and analog inputs. They should be isolated
as much as possible. Rise and fall times should be as large as possible to
minimize ac coupling effects.
7
6
5
4
3
2
1
0
Field
—
PQB3
(AN3)
(ANZ)
PQB2
(AN2)
(ANY)
PQA1
(AN1)
(ANX)
PQA0
(AN0)
(ANW)
Reset
0000
See Note
R/W:
R
R/W
Address
IPSBAR + 0x19_0007
Figure 28-5. QADC Port QB Data Register (PORTQB)
7
6
5
4
3
2
1
0
Field
—
DDQA4
DDQA3
—
DDQA1
DDQA0
Reset
0000_0000
R/W:
R
R/W
R
R/W
Address
IPSBAR + 0x19_0008
Figure 28-6. QADC Port QA Data Direction Register (DDRQA)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3