Motorola ColdFire MCF5281 - Manual (Page 565)

Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor 28-27
28.6.8 Result Registers
The result word table is a 64 half-word (128 byte) long by 10-bit wide RAM. An entry is written by the
QADC after completing an analog conversion specified by the corresponding CCW table entry.
28.6.8.1 Right-Justified Unsigned Result Register (RJURR)
28.6.8.2 Left-Justified Signed Result Register (LJSRR)
1
All channels not listed are reserved or unimplemented and return undefined results.
15 10 9 8
Field — RESULT
Reset 0000_00 Undefined
R/W: R R/W
7 0
Field RESULT
Reset Undefined
R/W: R/W
Address IPSBAR + 0x19_0280, 0x19_02fe
Figure 28-15. Right-Justified Unsigned Result Register (RJURR)
Table 28-18. RJURR Field Descriptions
Bit(s) Name Description
15–10 — Reserved, should be cleared.
9–0 RESULT The conversion result is unsigned, right-justified data.
15 14 8
Field S RESULT
Reset Undefined
R/W: R/W
7 0
Field RESULT
Reset Undefined
R/W: R/W
Address IPSBAR + 0x19_0300, 0x19_037e
Figure 28-16. Left-Justified Signed Result Register (LJSRR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3