Motorola ColdFire MCF5281 - Manual (Page 71)

ColdFire Core
Freescale Semiconductor 2-25
2.3.5 Instruction Execution Timing
This section presents processor instruction execution times in terms of processor-core clock cycles. The
number of operand references for each instruction is enclosed in parentheses following the number of
processor clock cycles. Each timing entry is presented as C(R/W) where:
• C is the number of processor clock cycles, including all applicable operand fetches and writes, and
all internal core cycles required to complete the instruction execution.
27–24
CCSZ Configurable cache size. Indicates the amount of instruction/data cache. The cache configuration options
available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register.
0000 No configurable cache
0001 512B configurable cache
0010 1KB configurable cache
0011 2KB configurable cache (This is the value used for this device)
0100 4KB configurable cache
0101 8KB configurable cache
0110 16KB configurable cache
0111 32KB configurable cache
Else Reserved
23–19
FLASHSZ
Flash bank size.
0000-0111 No flash
1000 64-KB flash
1001 128-KB flash
1010 256-KB flash
1011 512-KB flash (This is the value used for this device)
Else Reserved for future use.
18–16 Reserved
15–14
MBSZ Bus size. Defines the width of the ColdFire master bus datapath.
00
32-bit system bus datapath (This is the value used for this device)
01 64-bit system bus datapath
Else Reserved
13–8 Reserved, resets to 0b010000
7–3
SRAMSZ
SRAM bank size.
00000 No SRAM
00010 512 bytes
00100 1 KB
00110 2 KB
01000 4 KB
01010 8 KB
01100 16 KB
01110 32 KB
10000 64 KB (This is the value used for this device)
10010 128 KB
Else
Reserved for future use
2–0 Reserved.
Table 2-10. D1 Hardware Configuration Information Field Description (continued)
Field Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3