Motorola ColdFire MCF5281 - Manual (Page 737)

Freescale Semiconductor B-1
Appendix B
Revision History
This appendix lists major changes between versions of the MCF5282UM document.
B.1 Changes Between Rev. 0 and Rev. 0.1
Table B-1. Rev. 0 to Rev. 0.1 Changes
Location Description
Title page Changed title from “MCF5282 ColdFire
®
Integrated Microprocessor User’s Manual” to “MCF5282
ColdFire
®
Microcontroller User’s Manual.”
33.1/33-1 Added “This product incorporates SuperFlash® technology licensed from SST.”
Table 9-4 on page
9-6
Changed equation in footnote to f
sys
= f
ref
×
2(MFD + 2)/2 exp RFD; f
ref
×
2(MFD + 2)
≤
80 MHz, f
sys
≤
66
MHz.
Table 9-4 on page
9-6
Multiplied all PLL frequencies in table by 2.
Table 10-13 on
page 10-13
Changed DTMRx to DTIMx.
Figure 10-1 on
page 10-6
Changed bit numbers from 63–32 to 31–0.
Figure 10-3 on
page 10-8
Changed bit numbers from 63–32 to 31–0.
Figure 10-5 on
page 10-10
Changed bit numbers from 63–32 to 31–0.
14.2.4/14-22 Added Section 14.2.4, “Chip Configuration Signals .”
Table 14-3 on
page 14-11
Added Table 14-3 .
15.2/15-3 Added “Unlike the MCF5272, the MCF5282 does not have an independent SDRAM clock signal. For the
MCF5282, the timing of the SDRAM controller is controlled by the CLKOUT signal.”
15.2.3.2/15-13 Added Section 15.2.3.2, “SDRAM Byte Strobe Connections .”
15.2.3.1/15-9 Added “Note: Because the MCF5282 has 24 external address lines, the maximum SDRAM address size
is 128 Mbits.”
Figure 27-4 on
page 27-6
Changed reset value to 0010_0000_0000_0000.
Chapter 30,
“Debug Support ”
Changed “PSTCLK” references to “CLKOUT.”
Figure 30-41 on
page 30-45
Changed “TEA” to “TA.”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3