Motorola ColdFire MCF5281 - Manual (Page 743)

Revision History
Freescale Semiconductor B-7
B.4 Changes Between Rev. 2 and Rev. 2.1
B.5 Changes Between Rev. 2.1 and Rev. 2.2
B.6 Changes Between Rev. 2.2 and Rev. 2.3
Table B-4. Rev. 2 to Rev. 2.1 Changes
Location Description
Title Page Added MCF5280 to “Devices Supported” list on the title page.
Table 33-8/33-9 Deleted reference to “TA=TL to TH”
Table B-5. Rev. 2.1 to Rev. 2.2 Changes
Location Description
Chapter 33 Added Power Spec info to Electricals chapter
Table B-6. Rev. 2.2 to Rev. 2.3 Changes
Location Description
Figure 4-2/4-6 Changed bit 23 from DIDI to DISI
Table 4-6/4-9 Under ‘Configuration’ for ‘Instruction Cache’ the ‘Operation’ entry changed to “Invalidate 2 KByte data
cache”
Table 4-6/4-9 Under ‘Configuration’ for ‘Data Cache’ the ‘Operation’ entry changed to “Invalidate 2 KByte instruction
cache”
Figure 6-3/6-6 Changed bit 8 to write-only instead of read/write
Table 6-10/6-15 Removed “selected by BKSL[1:0]” as these are internal signal names not necessary for end-user.
10.3.2/10-8 Added note after register descriptions: ‘If an interrupt source is being masked in the interrupt controller
mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the status register
(SR[I]) is set to a value lower than the interrupt’s level, a spurious interrupt may occur. This is because by
the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious
interrupt is generated because the CPU cannot determine the interrupt source. To avoid this situation for
interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before
setting the mask in the IMR or the module’s interrupt mask register. After the mask is set, return the
interrupt mask in the status register to its previous value. Since level seven interrupts cannot be disabled
in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level
seven interrupts is not recommended.
Table 17-2/17-5 In PALR/PAUR entry, deleted “(only needed for full duplex flow control)”
Figure
17-23/17-39
Changed FRSR to read/write instead of read-only
25.4.10/25-16 Changed CANICR to ICRn
Table 25-17/25-29 Added the following information to BITERR and ACKERR descriptions: “To clear this bit, first read it as a
one, then write it as a one. Writing zero has no effect.”
Table 25-17/25-30 Changed bit ordering: ERRINT should be bit 2 and BOFFINT should be bit 1.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3