Motorola ColdFire MCF5281 - Manual (Page 99)

Freescale Semiconductor 4-1
Chapter 4
Cache
4.1 Introduction
This chapter describes cache operation on the ColdFire processor.
4.1.1 Features
Features include the following:
• Configurable as instruction, data, or split instruction/data cache
• 2 -Kbyte direct-mapped cache
• Single-cycle access on cache hits
• Physically located on the ColdFire core's high-speed local bus
• Nonblocking design to maximize performance
• Separate instruction and data 16-Byte line-fill buffers
• Configurable instruction cache miss-fetch algorithm
4.1.2 Introduction
The cache is a direct-mapped, single-cycle memory. It may be configured as an instruction cache, a
write-through data cache, or a split instruction/data cache. The cache storage is organized as
128 lines,
each containing 16 bytes. The memory storage consists of a 128 -entry tag array (containing addresses and
a valid bit), and a data array containing 2 Kbytes, organized as 512
× 32 bits.
Cache configuration is controlled by bits in the cache control register (CACR), detailed later in this
chapter. For the instruction or data-only configurations, only the associated instruction or data line-fill
buffer is used. For the split cache configuration, one-half of the tag and storage arrays is used for an
instruction cache and one-half is used for a data cache. The split cache configuration uses the instruction
and the data line-fill buffers. The core’s local bus is a unified bus used for instruction and data fetches.
Therefore, the cache can have only one fetch, instruction or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in parallel:
fetch address bits [
10 :4] addressing the tag array, and fetch address bits [ 10 :2] addressing the storage array.
For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the
tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [
9 :4]
provide the rest of the tag array address. The tag array outputs the address mapped to the given cache
location along with the valid bit for the line. This address field is compared to bits [31:
11 ] for instruction-
or data-only configurations and to bits [31: 10 ] for a split configuration of the fetch address from the local
bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3