Document Outline

• TMP92CZ26AXBG
  • 1. Outline and Features
  • 2. Pin Assignment and Pin Functions
    • 2.1 Pin Assignment Diagram (Top View)
    • 2.2 Pin names and Functions
  • 3. Operation
    • 3.1 CPU
      • 3.1.1 CPU Outline
      • 3.1.2 Reset Operation
      • 3.1.3 Setting of AM0 and AM1
    • 3.2 Memory Map
    • 3.3 Clock Function and Standby Function
      • 3.3.1 Block diagram of system clock
      • 3.3.2 SFR
      • 3.3.3 System clock controller
      • 3.3.4 Clock doubler (PLL)
      • 3.3.5 Noise reduction circuits
      • 3.3.6 Standby controller
    • 3.4 Boot ROM
      • 3.4.1 Operation Modes
      • 3.4.2 Hardware Specifications of Internal Boot ROM
      • 3.4.3 Outline of Boot Operation
      • 3.4.4 Downloading a User Program via UART
      • 3.4.5 Downloading a User Program via USB
    • 3.5 Interrupts
      • 3.5.1 General-purpose Interrupt Processing
      • 3.5.2 Micro DMA processing
      • 3.5.3 Interrupt Controller Operation
    • 3.6 DMAC (DMA Controller)
      • 3.6.1 Block Diagram
      • 3.6.2 SFRs
      • 3.6.3 DMAC Operation Description
      • 3.6.4 Setting Example
      • 3.6.5 Note
      • 3.6.6 Considerations for Using More Than One Bus Master
    • 3.7 Function of ports
      • 3.7.1 Port 1 (P10 to P17)
      • 3.7.2 Port 4 (P40 to P47)
      • 3.7.3 Port 5 (P50 to P57)
      • 3.7.4 Port 6 (P60 to P67)
      • 3.7.5 Port 7 (P70 to P76)
      • 3.7.6 Port 8 (P80 to P87)
      • 3.7.7 Port 9 (P90 to P92, P96, P97)
      • 3.7.8 Port A (PA0 to PA7)
      • 3.7.9 Port C (PC0 to PC7)
      • 3.7.10 Port F (PF0 to PF5, PF7)
      • 3.7.11 Port G (PG0 to PG5)
      • 3.7.12 Port J (PJ0 to PJ7)
      • 3.7.13 Port K (PK0 to PK7)
      • 3.7.14 Port L (PL0 to PL7)
      • 3.7.15 Port M (PM1, PM2, PM7)
      • 3.7.16 Port N (PN0 to PN7)
      • 3.7.17 Port P (PP1 to PP7)
      • 3.7.18 Port R (R0 to R3)
      • 3.7.19 Port T (PT0 to PT7)
      • 3.7.20 Port U (PU0 to PU7)
      • 3.7.21 Port V (PV0 to PV4, PV6, PV7)
      • 3.7.22 Port W (PW0 to PW7)
      • 3.7.23 Port X (PX4, PX5 and PX7)
      • 3.7.24 Port Z (PZ0 to PZ7)
    • 3.8 Memory Controller (MEMC)
      • 3.8.1 Functions
      • 3.8.2 Control register and Operation after reset release
      • 3.8.3 Basic functions and register setting
      • 3.8.4 ROM Page mode Access Control
      • 3.8.5 Internal Boot ROM Control
      • 3.8.6 Cautions
    • 3.9 External Memory Extension Function (MMU)
      • 3.9.1 Recommended memory map
      • 3.9.2 Control register
        • 3.9.2.1 Program bank register
        • 3.9.2.2 LCD display bank register
        • 3.9.2.3 Read-data bank register
        • 3.9.2.4 Write-data bank register
        • 3.9.2.5 DMA-function bank register
      • 3.9.3 Setting example
    • 3.10 SDRAM Controller (SDRAMC)
      • 3.10.1 Control Registers
      • 3.10.2 Operation Description
      • 3.10.3 An Example of Calculating HDMA Transfer Time
      • 3.10.4 Considerations for Using the SDRAMC
    • 3.11 NAND Flash Controller (NDFC)
      • 3.11.1 Features
      • 3.11.1 Block Diagram
      • 3.11.2 Operation Description
        • 3.11.2.1 Accessing NAND Flash Memory
      • 3.11.3 ECC Control
        • 3.11.3.1 Differences between Hamming Codes and Reed-Solomon Codes
        • 3.11.3.2 Error Correction Methods
      • 3.11.4 Description of Registers
      • 3.11.5 An Example of Accessing NAND Flash of SLC Type
      • 3.11.6 An Example of Accessing NAND Flash of MLC Type (When the valid data is processed as 518byte)
      • 3.11.7 An Example of Connections with NAND Flash
    • 3.12 8 Bit Timer (TMRA)
      • 3.12.1 Block Diagram
      • 3.12.2 Operation of Each Circuit
      • 3.12.3 SFR
      • 3.12.4 Operation in Each Mode
    • 3.13 16 bit timer / Event counter (TMRB)
      • 3.13.1 Block diagram
      • 3.13.2 Operation
      • 3.13.3 SFR
      • 3.13.4 Operation in Each Mode
    • 3.14 Serial Channels (SIO)
      • 3.14.1 Block Diagram
      • 3.14.2 Operation of Each Circuit
      • 3.14.3 SFR
      • 3.14.4 Operation in each mode
      • 3.14.5 Support for IrDA
    • 3.15 Serial Bus Interface (SBI)
      • 3.15.1 Configuration
      • 3.15.2 Serial Bus Interface (SBI) Control
      • 3.15.3 The Data Formats in the I2C Bus Mode
      • 3.15.4 I2C Bus Mode Control Register
      • 3.15.5 Control in I2C Bus Mode
      • 3.15.6 Data Transfer in I2C Bus Mode
    • 3.16 USB Controller
      • 3.16.1 Outline
        • 3.16.1.1 System Configuration
        • 3.16.1.2 Example
      • 3.16.2 900/H1 CPU I/F
        • 3.16.2.1 SFRs
        • 3.16.2.2 USBCR1 Register
        • 3.16.2.3 USBINTFRn, MRn Register
      • 3.16.3 UDC CORE
        • 3.16.3.1 SFRs
        • 3.16.3.2 EPx_FIFO Register (x: 0 to 3)
        • 3.16.3.3 bmRequestType Register
        • 3.16.3.4 bRequest Register
        • 3.16.3.5 wValue Register
        • 3.16.3.6 wIndex Register
        • 3.16.3.7 wLength Register
        • 3.16.3.8 Setup Received Register
        • 3.16.3.9 Current_Config Register
        • 3.16.3.10 Standard Request Register
        • 3.16.3.11 Request Register
        • 3.16.3.12 DATASET Register
        • 3.16.3.13 EPx_STATUS Register (x: 0 to 7)
        • 3.16.3.14 EPx_SIZE Register (x: 0 to 7)
        • 3.16.3.15 FRAME Register
        • 3.16.3.16 ADDRESS Register
        • 3.16.3.17 EOP Register
        • 3.16.3.18 Port Status Register
        • 3.16.3.19 Standard Request Mode Register
        • 3.16.3.20 Request Mode Register
        • 3.16.3.21 COMMAND Register
        • 3.16.3.22 INT_Control Register
        • 3.16.3.23 USB STATE Register
        • 3.16.3.24 EPx_MODE Register (x: 1 to 3)
        • 3.16.3.25 EPx_SINGLE Register
        • 3.16.3.26 EPx_BCS Register
        • 3.16.3.27 USBREADY Register
        • 3.16.3.28 Set Descriptor STALL Register
        • 3.16.3.29 Descriptor RAM Register
      • 3.16.4 Descriptor RAM
      • 3.16.5 Device Request
        • 3.16.5.1 Standard request
        • 3.16.5.2 Printer Class Request
        • 3.16.5.3 Vendor request (Class request)
      • 3.16.6 Transfer mode and Protocol Transaction
      • 3.16.7 Bus Interface and Access to FIFO
      • 3.16.8 USB Device answer
      • 3.16.9 Power Management
      • 3.16.10 Supplement
      • 3.16.11 Points to Note and Restrictions
    • 3.17 SPIC (SPI Controller)
      • 3.17.1 Block diagram
      • 3.17.2 SFR
    • 3.18 I2S (Inter-IC Sound)
      • 3.18.1 Block Diagram
      • 3.18.2 SFRs
      • 3.18.3 Description of Operation
      • 3.18.4 Detailed Description of Operation
    • 3.19 LCD Controller (LCDC)
      • 3.19.1 LCDC Features according to LCD Driver Type
      • 3.19.2 SFRs
      • 3.19.3 Description of Operation
        • 3.19.3.1 Outline
        • 3.19.3.2 Display Memory Mapping
        • 3.19.3.3 Basic Operation
        • 3.19.3.4 Reference Clock LCP0
        • 3.19.3.5 Refresh Rate
        • 3.19.3.6 Signal Settings
      • 3.19.4 Interrupt Function
      • 3.19.5 Special Functions
        • 3.19.5.1 PIP (Picture in Picture) Function
        • 3.19.5.2 Display Data Rotation Function
        • 3.19.5.3 Considerations for Using the LCDC
      • 3.19.6 Setting Example
    • 3.20 Touch Screen Interface (TSI)
      • 3.20.1 Touch-Screen Interface Module Internal/External Connection
      • 3.20.2 Touch Screen Interface (TSI) Control Register
      • 3.20.3 Touch detection procedure
      • 3.20.4 X/Y position measuring procedure
      • 3.20.5 Flow chart for TSI
      • 3.20.6 Note
    • 3.21 Real time clock (RTC)
      • 3.21.1 Function description for RTC
      • 3.21.2 Block diagram
      • 3.21.3 Control registers
      • 3.21.4 Detailed explanation of control register
      • 3.21.5 Operational description
      • 3.21.6 Explanation of the interrupt signal and alarm signal
    • 3.22 Melody / Alarm generator (MLD)
      • 3.22.1 Block Diagram
      • 3.22.2 Control registers
      • 3.22.3 Operational Description
        • 3.22.3.1 Melody generator
        • 3.22.3.2 Alarm generator
    • 3.23 Analog-Digital Converter (ADC)
      • 3.23.1 Control register
      • 3.23.2 Operation
        • 3.23.2.1 Analog Reference Voltages
        • 3.23.2.2 Analog Input Channel(s) selection
        • 3.23.2.3 Starting an AD Conversion
        • 3.23.2.4 AD Conversion Modes and AD Conversion-End Interrupts
        • 3.23.2.5 High-Priority Conversion Mode
        • 3.23.2.6 AD Monitor Function
        • 3.23.2.7 AD Conversion Time
        • 3.23.2.8 Storing and Reading the AD Conversion Result
        • 3.23.2.9 Data Polling
    • 3.24 Watchdog Timer (Runaway detection timer)
      • 3.24.1 Configuration
      • 3.24.2 Operation
      • 3.24.3 Control Registers
    • 3.25 Power Management Circuit (PMC)
      • 3.25.1 SFR
      • 3.25.2 Detailed Description of Operation
      • 3.25.3 Detailed Description of Timing
      • 3.25.4 Notes of Power sequence
      • 3.25.5 Setting Example
    • 3.26 Multiply and Accumulate Calculation Unit (MAC)
      • 3.26.1 Registers
        • 3.26.1.1 Control Register
        • 3.26.1.2 Data Registers
      • 3.26.2 Description of Operation
      • 3.26.3 Operation Examples
    • 3.27 Debug Mode
  • 4. Electrical Characteristics
    • 4.1 Maximum Ratings
    • 4.2 DC Electrical Characteristics
    • 4.3 AC Characteristics
      • 4.3.1 Basic Bus Cycle
      • 4.3.2 Page ROM Read Cycle
      • 4.3.3 SDRAM controller AC Characteristics
      • 4.3.4 NAND Flash Controller AC Characteristics
      • 4.3.5 Serial channel timing
      • 4.3.6 Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0)
      • 4.3.7 Interrupt Operation
      • 4.3.8 USB Timing (Full-speed)
      • 4.3.9 LCD Controller
      • 4.3.10 I2S Timing
      • 4.3.11 SPI Controller
    • 4.4 AD Conversion Characteristics
  • 5. Table of Special function registers (SFRs)
  • 6. Package