Toshiba H1 Series - Manual (Page 360)

TMP92CZ26A
92CZ26A-357
3.15.6 Data Transfer in I
2
C Bus Mode
(1) Device initialization
Set the SBICR1<ACK, SCK2:0>, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the
SBICR1 to “0”.
Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format)
to the I2CAR.
For specifying the default setting to a slave receiver mode, clear “0” to the <MST, TRX,
BB> and set “1” to the <PIN>, “10” to the <SBIM1:0>.
7 6 5 4 3 2 1 0
SBICR1 ← 0 0 0 X 0 X X X Set acknowledge and SCL clock.
I2CAR
← X X X X X X X X
Set slave address and address recognition mode.
SBICR2
← 0 0 0 1 1 0 0 0
Set to slave receiver mode.
Note: X: Don’t care
(2) Start condition and slave address generation
a. Master Mode
In the Master Mode, the start condition and the slave address are generated as
follows.
Check a bus free status (when <BB>
= “0”).
Set the SBICR1<ACK> to “1” (Acknowledge Mode) and specify a slave address
and a direction bit to be transmitted to the SBIDBR.
When SBICR2<BB>
= “0”, the start condition are generated by writing “1111” to
SBICR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address and
the direction bit which are set to the SBIDBR. At the 9th clock, the SDA line is
released and the acknowledge signal is received from the slave device.
An INTSBI interrupt request occurs at the falling edge of the 9th clock. The
<PIN> is cleared to “0”. In the Master Mode, the SCL pin is pulled down to the
Low-level while <PIN> is “0”. When an interrupt request occurs, the <TRX> is
changed according to the direction bit only when an acknowledge signal is
returned from the slave device.
Setting in main routine
7 6 5 4 3 2 1 0
Reg.
← SBISR
Reg. ← Reg. e 0x20
if Reg.
≠ 0x00
Wait until bus is free.
Then
SBICR1
← X X X 1 X X X X
Set to acknowledgement mode.
SBIDBR1 ← X X X X X X X X Set slave address and direction bit.
SBICR2
← 1 1 1 1 1 0 0 0
Generate start condition.
In INTSBI interrupt routine
INTCLR
← 0X2a
Clear the interrupt request
Process
End of interrupt