Toshiba H1 Series - Manual (Page 192)

TMP92CZ26A
92CZ26A-189
(2) Connection Memory Specification
Setting BnCSH<BnOM1:0> specifies the memory type to be connected with the block
address areas. The interface signal is output according to the set memory as follows;
BnCSH<BnOM1:0>
BnOM1 BnOM0 Function
0 0 SRAM/ROM (Default)
0 1 (Reserved)
1 0 (Reserved)
1 1 SDRAM
Note1: SDRAM should be set only with CS1 or CS2 .
(3) Data Bus Width Specification
The data bus width is set for every block address area. The bus size is set by
BnCSH<BnBUS1:0> as follows;
BnCSH<BnBUS1:0>
<BnBUS1> <BnBUS0> Function
0 0 8-bit bus mode (Default)
0 1 16-bit bus mode
1 0 Reserved
1 1 Don’t use this setting
Note1: SDRAM should be set to “01”(16-bit bus).
This way of changing the data bus width depending on the address being accessed is
called “dynamic bus sizing”. The part where the data is output to is depended on the data
width, the bus width and the start address.
The number of external data bus pin in TMP92CZ26A are 16 pin. Therefore, please
ignore the bus width of memory = 32 bit in the table.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus
width are put in consecutive address, do not execute a access to both memories with one command.