Toshiba H1 Series - Manual (Page 184)

TMP92CZ26A
92CZ26A-181
3.8.2 Control register and Operation after reset release
This section describes the registers to control the memory controller, the state after reset
release and necessary settings.
(1) Control Register
The control registers of the memory controller are as follows and Table 3.8.1 to Table 3.8.2.
Control register: BnCSH/BnCSL(n=0 to 3, EX)
Sets the basic functions of the memory controller that is the connecting memory
type, the number of waits to be read and written.
Memory start address register: MSARn(n=0 to 3)
Sets a start address in the selected address areas.
Memory address mask register: MAMR (n=0 to 3)
Sets a block size in the selected address areas.
Page ROM control register: PMEMCR
Sets to control Page-ROM.
Adjust the timing of control signal register: CSTMGCR, WRTMGCR, RDTMGCRn
Adjust the timing of rising/falling edge of control signals.
Internal-Boot ROM control register: BROMCR
Sets to access Boot-ROM.