Toshiba H1 Series - Manual (Page 651)

TMP92CZ26A
92CZ26A-648
(2) Write cycle (0 waits)
Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing . The CSn , R/ W , RD , WRxx , SRxxB , SRWR
pins timing can be adjusted by memory controller timing adjust function.
t
OSC
SDCLK
WAIT
A0~A23
D0~D15
SRxxB
X1
CSn
WRxx
SRWR
t
CL
t CYC
t
CH
t
TK
t
KT
t
WW
t DW
t
AW
t
WK
t SBW
Data output
t
WA
t
SWR
t
WD
RD
t RDO
t SDH
t
SAS
t
SWP
t SDS
R/ W