Toshiba H1 Series - Manual (Page 375)

TMP92CZ26A
92CZ26A-372
7 6 5 4 3 2 1 0
bit Symbol INT_URST_STR INT_URST_END INT_SUS INT_RESUME INT_CLKSTOP INT_CLKON
Read/Write R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0
Function When read 0: Not generate interrupt
1: Generate interrupt
When write 0: Clear flag
1:
−
Note: Above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode can not be released)
*Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, the system of low power
dissipation can be built. However, the way of use is limited as below.
Shift to IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
Release from IDLE1 mode :
Release Halt state by the request of INT_RESUME or INT_CLKON ( request of release SUSPEND )
Release Halt state by the request of INT_URST_STR or INT_URST_END ( request of RESET )
• INT_URST_STR (Bit7)
This is a flag for INT_URST_STR (“USB reset” start - interrupt).
This is set to “1” when the UDC started to receive “USB reset” signal from
USB-host.
An application program has to initialize whole UDC by this interrupt.
• INT_URST_END (Bit6)
This is a flag for INT_URST_END (“USB reset” end - interrupt).
This is set to “1” when the UDC receive “USB reset end” signal from
USB-host.
• INT_SUS (Bit5)
This is a flag for INT_SUS (suspend - interrupt).
This is set to “1” when USB change to “suspend status”.
• INT_RESUME (Bit4)
This is a flag for INT_RESUME (resume - interrupt).
This is set to “1” when USB change to “resume status”.
• INT_CLKSTOP (Bit3)
This is a flag for INT_CLKSTOP (enable stopping clock supply - interrupt).
This is set to “1” when USB enable stopping clock supply after changing to
“suspend status”.
• INT_CLKON (Bit2)
This is a flag for INT_CLKON (enabled starting clock supply - interrupt).
This is set to “1” when USB enable starting clock supply after change to
“resume status”.
USBINTFR1
(07F0H)
Prohibit
to read
modify
write