Toshiba H1 Series - Manual (Page 273)

TMP92CZ26A
92CZ26A-270
Figure 3.12.4 TMRA67 Block Diagram
φT1
φT16
φT256
8-bit comparato
r
(CP7)
8-bit comparato
r
(CP6)
8-bit up counter
(UC6)
2
n
Ov
er
flow
8-bit
up comparato
r
(UC7)
Ti
mer
flip-
flop
TA7FF
Match detect
Match detect
8-bit timer
register
TA7REG
φT1 φT4
φT16
512
256
128
64
32
16
8
4
2 φT1
φT4
φT16
φT256
Run/clea
r
Pr
escale
r
TA67MOD <TA6CLK1:0>
Pr
escale
r
clock φT0
TMR
TA67RUN<
TA6
RUN>
Selecto
r
8-bit timer regist
er
TA6REG
TA67MOD <PWM61:60>
TA67MOD <TA67M1:0>
TMRA6 Interrup
t output:
INTTA6
TMRA6 Interrup
t output:
TA6TR
G
TA67MOD <TA7CLK1:0>
TA67RUN<
TA7
RUN>
TA7FF
CR
Ti
mer fl
ip
-fl
op
output: TA7
O
UT
TMRA7 Interrup
t output:
INTTA7
Internal data bus
TA67RUN <TA6RDE>
TA67RUN <TA67PRUN>
Selecto
r
Internal data bus
T
A
6T
R
G
Register buffer 6
Low- frequency clock (
fs)