Toshiba H1 Series - Manual (Page 38)

TMP92CZ26A
92CZ26A-35
The operation of each of the different Halt Modes is described in Table 3.3.3.
Table 3.3.3 I/O operation during Halt Modes
Halt Mode IDLE2 IDLE1 STOP
SYSCR2 <HALTM1:0> 11 10 01
CPU, MAC Stop
I/O ports Depends on PxDR register setting
TMRA, TMRB
SIO,SBI
A/D converter
WDT
Available to select
Operation block
I2S, LCDC, SDRAMC,
Interrupt controller,
SPIC , DMAC, NDFC,
USB
Stop
Block
RTC, MLD
Operate
Operate
(2) How to release the Halt mode
These HALT states can be released by resetting or requesting an interrupt. The halt
release sources are determined by the combination between the states of interrupt
mask register <IFF2:0> and the halt modes. The details for releasing the HALT status
are shown in Table 3.3.4.
• Released by requesting an interrupt
The operating released from the halt mode depends on the interrupt enabled status.
When the interrupt request level set before executing the HALT instruction exceeds
the value of interrupt mask register, the interrupt due to the source is processed after
releasing the halt mode, and CPU status executing an instruction that follows the
HALT instruction. When the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, releasing the halt
mode is not executed.(in non-maskable interrupts, interrupt processing is processed
after releasing the halt mode regardless of the value of the mask register.) However
only for INT0 to INT5, INT6, INT7(unsynchronous interrupt), INTKEY,INTRTC,
INTALM interrupts, even if the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, releasing the halt
mode is executed. In this case, interrupt processing, and CPU starts executing the
instruction next to the HALT instruction, but the interrupt request flag is held at “1”.
• Releasing by resetting
Releasing all halt status is executed by resetting.
When the STOP mode is released by RESET, it is necessary enough resetting time to
set the operation of the oscillator to be stable.
When releasing the halt mode by resetting, the internal RAM data keeps the state
before the “HALT” instruction is executed. However the other settings contents are
initialized. (Releasing due to interrupts keeps the state before the “HALT” instruction
is executed.)