Toshiba H1 Series - Manual (Page 449)

TMP92CZ26A
92CZ26A-446
When it writes data to FIFO in transmitting, confirm condition of two packets,
and consider the order of priority. When transfer data number is set, set to which
packet A and packet B, judge by PACKET_ACTIVE bit. Packet that bit is set to 0 is
bit that transfer now.
In transmitting and receiving, logic of PACKET_ACTIVE bit is reversed.
Therefore, please caution in transmitting.
Below is this sequence.
Figure 3.16.18 Transmitting Sequence in Dual Packet Mode
IDLE
Transmitting event
DATASET
= 1
Wait transmitting event
DATASETregister
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
Transmittind
data distinction
Transmitting number < payload
× 2
• Write number of transmitting
number
• Total = 0
EOP register
Write 0 to only bit of applicable
endpoint
If transmitting number reach to
payload, DATASET set 1 to
applicable bit of register
Wait transmitting
Finish
transmitting
If transmitting finish normally,
It clears applicable
bit of DATASET.
Wait
transmitting
rest data
Wait IN token
DATASET
= 0
• Accessing to EOP register is needed in
transmitting short packet
• Control transfer type is only single mode
Interrupt by EPx_EMPTY_A (B)
Check DATASET register
Transmitting number > payload
× 2
• Write number of payload × 2 in
applicable endpoint
• Total = Total − payload Ч 2