Toshiba H1 Series - Manual (Page 271)

TMP92CZ26A
92CZ26A-268
Figure 3.12.2 TMRA23 Block Diagram
φT1
φT16
φT256
8-bit comparato
r
(CP3)
8-bit comparato
r
(CP2)
8-bit up counter
(UC2)
2
n
Ov
er
flow
8-bit
up comparato
r
(UC3)
Ti
mer
flip-
flop
TA3FF
Match detect
Match detect
8-bit timer
register
TA3REG
φT1 φT4
φT16
512
256
128
64
32
16
8
4
2 φT1
φT4
φT16
φT256
Run/clea
r
Pr
escale
r
TA23MOD <TA2CLK1:0>
Pr
escale
r
clock φT0
TMR
TA23RUN<
TA2
RUN>
Selecto
r
8-bit timer regist
er
TA2REG
TA23MOD <PWM21:20>
TA23MOD <TA23M1:0>
TMRA2 Interrup
t output:
INTTA2
TMRA2 Interrup
t output:
TA2TR
G
TA23MOD <TA3CLK1:0>
TA23RUN<
TA3
RUN>
TA3FF
CR
T
imer
flip-
flop
output: TA3
O
UT
TMRA3 Interrup
t output:
INTTA3
Internal data bus
TA23RUN <TA2RDE>
TA23RUN <TA23PRUN>
Selecto
r
Internal data bus
TA2
TRG
Register buffer 2
External input
clock: T
A2IN