Toshiba H1 Series - Manual (Page 198)

TMP92CZ26A
92CZ26A-195
(7) Basic bus timing
(a) External read/write cycle (0 waits)
(b) External read/write cycle (1 wait)
CSn
WRxx
RD , SRxxB
A23 to A0
Input
Output
Read
Write
SDCLK
(60 MHz)
D15 to D0
D15 to D0
T1 T2
SRWR , SRxxB
CSn
WRxx
RD , SRxxB
A23 to A0
Output
SDCLK
(60 MHz)
D15 to D0
D15 to D0
T1 TW
Input
Read
Write
T2
SRWR , SRxxB