13 epx_status register (x: 0 to 7) – Toshiba H1 Series User Manual
Page 393
TMP92CZ26A
92CZ26A-390
3.16.3.13 EPx_STATUS Register (x: 0 to 7)
These registers are status registers for each endpoint. The <SUSPEND> is common
for all endpoint.
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
7
6
5
4
3
2 1 0
bit Symbol
TOGGLE SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Read/Write
R R
R
R R R R
After reset
0
0
1
1
1
0
0
Note: EP4, 5, 6 and 7_STATUS registers are not used TMP92CZ26A.
TOGGLE Bit (Bit6)
0:
TOGGLE
Bit0
1:
TOGGLE
Bit1
This bit shows status of toggle sequence bit.
SUSPEND (Bit5)
0:
RESUME
1:
SUSPEND
This bit shows status of power management of UDC.
In the SUSPEND status, some limitation about accessing to
UDC is needed.
For the detail, refer 3.10.9.
EP0_STATUS
(0790H)
EP1_STATUS
(0791H)
EP2_STATUS
(0792H)
EP3_STATUS
(0793H)
EP4_STATUS
(0794H)
EP5_STATUS
(0795H)
EP6_STATUS
(0796H)
EP7_STATUS
(0797H)