2 sfrs, The i, Figure 3.18.2 i – Toshiba H1 Series User Manual

Page 501: S channel 0 control registers

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TMP92CZ26A

92CZ26A-498

3.18.2 SFRs

The I

2

S unit is provided with the following registers. These registers are connected to the

CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be accessed
using 4-byte load instructions.

I2S0 Control Register

7 6 5 4 3 2 1 0

bit Symbol

TXE0 *CNTE0

DIR0 BIT0

DTFMT01

DTFMT00

SYSCKE0

Read/Write

R/W R/W

R/W R/W R/W R/W R/W

After reset

0 0 0 0 0 0 0

Function

Transmission

0: Stop

1: Start

Counter

control

0: Clear

1: Start

Transmissio

n start bit

0:MSB

1:LSB

Bit length

0: 8 bits

1: 16 bits

Output format

00: I

2

S 10:

Right

01: Left 11: Reserved

System

clock
0: Disable
1: Enable

15 14 13 12 11 10 9 8

bit Symbol

CLKS0

FSEL0 TEMP0

WLVL0

EDGE0 CLKE0

Read/Write

R/W R/W

R

R/W

R/W

R/W

After reset

0 0 1 0 0 0

Function

Source

clock

0: f

SYS

1: f

PLL

Stereo

/monaural

0: Stereo

1: Monaural

Transmissio

n FIFO state

0: Data

1: No data

WS level

0: Low left

1: High left

Data output

clock edge

0: Falling

1: Rising

Clock

operation

(after

transmis-

sion)

0: Enable

1: Disable

I2S0 Divider Value Setting Register

7 6 5 4 3 2 1 0

bit Symbol

CK07

CK06

CK05 CK04 CK03 CK02 CK01 CK00

Read/Write

R/W R/W R/W R/W R/W R/W R/W R/W

After

reset

0 0 0 0 0 0 0 0

Function

Divider value for CK signal (8-bit counter)

15 14 13 12 11 10 9 8

Bit

symbol

WS05 WS04 WS03 WS02 WS01 WS00

Read/Write

R/W R/W R/W R/W R/W R/W

After reset

0

0

0

0

0

0

Function

Divider value for WS signal (6-bit counter)

I2S0 Buffer Register

15 14 13 12 11

10

9

8 7

6 5 4

3 2 1 0

bit Symbol

B015 B014 B013 B012 B011

B010

B009

B008

B007

B006

B005

B004

B003 B002 B001 B000

Read/Write W

After reset

Undefined

Function

Transmission buffer register (FIFO)

31 30 29 28 27

26

25

24

23

22

21

20

19 18 17 16

bit Symbol

B031 B030 B09 B028 B027

B026

B025

B024

B023

B022

B021

B020

B019 B018 B017 B016

Read/Write W

After reset

Undefined

Function

Transmission buffer register (FIFO)

Figure 3.18.2 I

2

S Channel 0 Control Registers

I2S0CTL

(1808H)

I2S0BUF
(1800H)

Read-modify-
write
instructions
cannot be
used.

I2S0C

(180AH)

(180BH)

(1809H)

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