Toshiba H1 Series - Manual (Page 530)

TMP92CZ26A
92CZ26A-527
1. LVSYNC Signal
The period of the vertical synchronization signal LVSYNC indicates the time for each
screen update (refresh rate). The LVSYNC period is defined as an integral multiple of
the period of the horizontal synchronization signal LHSYNC.
The LVSYNC period is calculated as the product of the value set in LCDVSP<LV 9:0>
and the LHSYNC period. The value to be set in LCDVSP<LV9:0> should be “common
size + number of dummy clocks” or larger for TFT and STN.
LVSYNC [s: period]
= LHSYNC [s: period] × (<LVP9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LVP9:0> + 1)
LCD V SYNC Pulse Register
7 6 5 4 3 2 1 0
bit Symbol LVP7 LVP6 LVP5 LVP4 LVP3 LVP2 LVP1 LVP0
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function LVSYNC period (bits 7-0)
7 6 5 4 3 2 1 0
bit Symbol LVP9 LVP8
Read/Write W
After reset 0 0
Function
LVSYNC period
(bits 9-8)
The enable width of the LVSYNC signal can be specified as 1 clock, 2 clocks, or 3
clocks of LHSYNC in LCDCTL1<LVSW1:0>.
The phase of the LVSYNC signal can be inverted by the setting of LCDCTL1
<LVSP>.
LCD Control 1 Register
7 6 5 4 3 2 1 0
bit Symbol LCP0P LHSP LVSP LLDP LVSW1 LVSW0
Read/Write R/W R/W R/W R/W R/W R/W
After reset 1 0 1 0 0 0
Function
LCP0
phase
0: Rising
1: Falling
LHSYNC
phase
0: Rising
1: Falling
LVSYNC
phase
0: Rising
1: Falling
LLOAD
phase
0: Rising
1: Falling
LVSYNC
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
LVSYNC signal
(Phase control)
(Enable width control)
LVSP=1
LVSP=0
Refresh rate
LCDVSP
(028CH)
(028DH)
LCDCTL1
(0286H)