Toshiba H1 Series - Manual (Page 650)

TMP92CZ26A
92CZ26A-647
(1) Read cycle (0 waits)
Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing . The CSn , R/ W , RD , WRxx , SRxxB , SRWR
pins timing can be adjusted by memory controller timing adjust function.
t OSC
SDCLK
WAIT
A0~A23
D0~D15
SRxxB
X1
CSn
RD
SRWR
t
CL
t CYC
t
CH
t
TK
t
KT
t AD
t
RR
t
RD
t
RRH
t AR t RK
t
SBA
Data input
t HA
t HR
R/ W