Toshiba H1 Series - Manual (Page 297)

TMP92CZ26A
92CZ26A-294
3.13 16 bit timer / Event counter (TMRB)
The TMP92CZ26A incorporates two multifunctional 16-bit timer/event counter (TMRB0,
TMRB1) which have the following operation modes:
• 16 bit interval timer mode
• 16 bit event counter mode
• 16 bit programmable pulse generation mode (PPG)
Can be used following operation modes by capture function.
• Frequency measurement mode
• Pulse width measurement mode
Timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (One of them
with a double-buffer structure), a 16-bit capture registers, two comparators, a capture input
controller, a timer flip-flop and a control circuit.
Timer/event counter is controlled by an 11-byte control SFR.Each channel(TMRB0,TMRB1)
operate independently.In this section, the explanation describes only for TMRB0 because each
channel is identical operation except for the difference as follows;
Table 3.13.1 Difference between TMRB0 and TMRB1
Channel
Specification
TMRB0 TMRB1
External clock/
capture trigger input pins TB0IN0
(Shared with PP4)
TB1IN0
(Shared with PP5) External
pins Timer flip-flop output pins TB0OUT0
(Shared with PP6)
TB1OUT0
(Shared with PP7)
Timer run register TB0RUN (1180H) TB1RUN (1190H)
Timer mode register TB0MOD (1182H) TB1MOD (1192H)
Timer flip-flop
control register
TB0FFCR (1183H) TB1FFCR (1193H)
TB0RG0L (1188H) TB1RG0L (1198H)
TB0RG0H (1189H) TB1RG0H (1199H)
TB0RG1L (118AH) TB1RG1L (119AH)
Timer register
TB0RG1H (118BH) TB1RG1H (119BH)
TB0CP0L (118CH) TB1CP0L (119CH)
TB0CP0H (118DH) TB1CP0H (119DH)
TB0CP1L (118EH) TB1CP1L (119EH)
SFR
(Address)
Capture register
TB0CP1H (118FH) TB1CP1H (119FH)