Toshiba H1 Series - Manual (Page 105)

TMP92CZ26A
92CZ26A-102
(2) CPU + LDMA
The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the
CPU and getting a bus acknowledgement.
If LDMA is not performed properly, the LCD display function cannot work properly.
Therefore, LDMA must have higher priority than the CPU. While LDMA is being
performed, the CPU cannot execute instructions.
To display data on the LCD using the LCD controller, it is necessary to estimate to what
degree LDMA would interfere with the CPU operation based on the display RAM type,
display RAM bus width, LCDD type, display pixel count, and display quality.
The time the CPU stops operation while the LCD controller transfers data for one line is
defined as “t
STOP
(LDMA)”, which is calculated as shown below for each display mode.
t
STOP
(LDMA) = (SegNum × K / 8) × t
LRD
16-bit external SRAM : t
LRD
= (2 + wait count) / f
SYS
[Hz] / 2
Internal RAM : t
LRD
= 1 / f
SYS
[Hz] / 4
16-bit external SDRAM :t
LRD
= 1 / f
SYS
[Hz] / 2
SegNum : Number of segments to be displayed
K : Number of bits needed for displaying 1 pixel
Monochrome K = 1
4 gray scales K = 2
16 gray scales K = 4
256 colors K = 8
4096 colors K = 12
65536 colors K = 16
262144/16777216 colors K = 24
Note 1: When SDRAM is used, the overhead time is added as shown below.
t
STOP
[s] = (SegNum
× K/8) × t
LRD
+ ((1/f
SYS
)
× 8)
Note 2: When internal RAM is used, the overhead time is added as shown below.
t
STOP
[s] = ( SegNum
× K/8 ) t
LRD
+ (1/f
SYS
)
The CPU bus stop rate indicates what proportion of the 1-line data update time
t
LP
is taken up by t
STOP
(LDMA) and is calculated as follows:
CPU bus stop rate = t
STOP
(LDMA) [s] / LHSYNC [period: s]