Toshiba H1 Series - Manual (Page 206)

TMP92CZ26A
92CZ26A-203
(2) Note the NAND flash area setting
Figure 3.8.8 shows a memory map for NAND flash.
And since CS3 area is recommended to assign address from 000000H to 3FFFFFH, this
case is explained.
In this case, “NAND flash” and CS3 area are overlapped. But 3 CS pin don’t become
active by setting BROMCR<CSDIS> to “1”. And also 0 CS to 3 CS , SDCS , CSXA to CSXB ,
CSZA to CSZD pins don’t become to active.
Note1: In this case, the address from 000000H to 049FFFH of 296 Kbytes in CS3’s memory can’t be used.
Note2: 16 byte area (001FF0H to 001FFFH) for NAND Flash are fixed like a following without relationship to
setting CS bock. Therefore, NAND flash area don’t according to CS3 area setting.
(NAND-Flash area specification)
1. bus width : Depend on NDFMCR1<BUSW> in NAND Flash controller.
2.WAIT control : Depend on NDFMCR<SPLW1:0>,<SPHW1:0> in NAND Flash controller
Figure 3.8.8 Recommended CS3 setting
NAND flash
(16 bytes)
COMMON X
(2 Mbytes)
LOCAL X
(2 Mbytes)
Internal I/O
Internal RAM
(288 Kbytes)
All CS pins become to unactibe
by BROMCR<CSDIS>
=”1”
000000H
001FF0H
002000H
400000H
04A000H
200000H
CS3 area setting
000000H to 3FFFFFH (4 Mbytes)