Toshiba H1 Series - Manual (Page 80)

TMP92CZ26A
92CZ26A-77
In
terru
p
t requ
e
s
t
s
ign
al to
C
P
U
IF
F
7
then
0
M
ic
ro D
M
A/
H
D
M
A
s
tar
t
v
e
ct
or
s
e
tt
in
g
re
gi
st
er
IN
TT
C4
/INT
D
M
A
4
IN
TT
C5
/INT
D
M
A
5
IN
TT
C6
IN
TT
C7
V
= E0H
V =
E4H
V =
E8H
V =
ECH
So
ft sta
rt
Micro DM
A
/H
D
M
A
c
o
unt
er 0
inte
rru
pt
6
IN
T
T
C0
/
IN
T
D
MA
0
Duri
ng
ID
L
E
1
52
3 3
3
6
1
7
3
3
8
6 51
8 i
n
pu
t OR
IN
T0
,1
t
o
4,
IN
T
K
E
Y
, IN
TR
T
C
IN
TA
LM
M
icr
o D
M
A
cha
n
n
e
l pr
ior
ity
en
co
rd
er
Pri
o
rit
y
e
n
cor
der
D
M
A0
V
D
M
A1
V
D
M
A2
V
D
M
A3
V
D
M
A4
V
D
M
A5
V
D
M
A6
V
D
M
A7
V
RE
SE
T
Int
e
rr
upt re
qu
est
F
/F
RE
SE
T
Dec
o
rder
Re
se
t
Prio
rity sett
ing
re
gister
V
= 20H
V
= 24H
Interrup
t c
o
ntroller
CP
U
S Q R
V
= 28H
V
= 2CH
V
= 30H
V
= 34H
V
= 38H
V
= 3CH
V
= 40H
V
= 44H
D Q
CL
R
Y1 Y2 Y3 Y4 Y5 Y6
A B C
Dn Dn +
1
Dn +
2
In
ter
rupt
re
qu
est F
/F
In
terrup
t v
e
c
tor read
Mi
cro D
M
A a
c
k
n
o
w
le
dg
e
Interrup
t reques
t
F/
F
Dn
+
3
A B C
In
terrup
t ve
c
tor
read
D2 D3 D4 D5 D6 D7
Se
le
cto
r
S
Q
R
0 1 2 7
A B C
D0 D1
In
ter
ru
p
t vecto
r
read
In
ter
rupt ma
sk
F/
F
Micro D
M
A
r
e
q
u
e
s
t
HA
L
T
r
e
le
a
s
e
IN
T
R
Q2
∼0
≥ IF
F
2
∼0 th
en
1.
INT
R
Q
2
to
0
IFF
2
to
0
In
te
rru
p
t
ma
sk
det
ect
RES
E
T EI
1
to
7
DI
In
terrup
t reques
t
sign
al
Duri
ng
STOP
Mic
ro DMA
c
h
a
n
nel
sp
eci
fic
a
ti
o
n
RE
SET
IN
T
W
D
INT0
INT
1
INT
2
INT
3
INT
4
INT
A
L
M
INT
T
A
4
INT
T
A
5
S
In
te
rr
up
t v
e
ct
or
g
ene
ra
tor
H
igh
est
pri
o
ri
ty
in
ter
rup
t
le
ve
l se
le
ct
1 2 3 4 5 6 7
D5 D4 D3 D2 D1 D0
D
Q
CL
R
HD
MA
3
6
6 i
n
pu
t OR
HD
MA ch
ann
el
p
rior
ity
en
co
rd
er
0 1 2 5
A B C
HDMA
re
que
s
t
HD
MA
channe
l
Mi
c
ro
D
M
A
/H
D
MA
sele
c
ti
o
n
regi
ste
r
6
Figure 3.5.3 Block Diagram of Interrupt Controller