Toshiba H1 Series User Manual
Page 130
TMP92CZ26A
92CZ26A-127
Port 7 register
7 6 5 4 3 2 1 0
bit
Symbol P76 P75 P74 P73 P72 P71 P70
Read/Write
R/W
After reset
Data from external port
(Output latch register is
set to “1”)
Data from external port
(Output latch register is
cleared to “0”)
Data from external port
(Output latch register is
set to “1”)
1
Port 7 Control register
7 6 5 4 3 2 1 0
bit
Symbol
P76C P75C P74C P73C P72C P71C
Read/Write
W
After
reset
0 0 0 0 0 0
Function
0: Input 1: Output
Port 7 Function register
7 6 5 4 3 2 1 0
bit Symbol
P76F
P75F
P74F P73F P72F P71F P70F
Read/Write
W
After
reset
0 0 0 0 0 0
0/1
Note3:
Function
0:Port
1: WAIT
Refer to following table
0:Port
1:
NDWE
at
<P72>=0
WRLU
at
<P72>=1
0:Port
1:
NDRE
at
<P71>=0
WRLL
at
<P71>=1
0:Port
1:
RD
Port 7 Drive register
7 6 5 4 3 2 1 0
bit Symbol
P76D P75D P74D P73D P72D P71D P70D
Read/Write
R/W
After
reset 1 1 1 1 1 1 1
Function
Input/Output buffer drive register for standby mode
Note1: Read-modify-write is prohibited for P7CR, P7FC.
Note2: When
NDRE
and
NDWE
are used, set registers by following order to avoid outputting negative glitch.
Order Registser
bit2
bit1
------------------------------------------------------
(1)
P7
0
0
(2) P7FC
1
1
(3) P7CR
1
1
Note3: Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.11 Register for Port7
P7
(001CH)
P7FC
(001FH)
P7CR
(001EH)
P7DR
(0087H)
<P71C>
>
<P71F>
0 1
0 Input
Port
Output
Port
1
Reserved
NDRE
Output
(at <P71>=0)
WRLL
Output
(at <P71>=1)
P71 setting
<
<P72C>
<P72F>
0 1
0 Input
Port
Output
Port
1
Reserved
NDWE
Output
(at <P72>=0)
WRLU
Output
(at <P72>=1)
P72 setting
P75 setting
<P76C>
<P76F>
0 1
0 Input
Port
Output
Port
1
WAIT Input
Reserved
P76 setting
<
<P73C>
<P73F>
0 1
0 Input
Port
Output
Port
1
Reserved EA24Output
P73 setting
P74 setting
<P75C>
<P75F>
0 1
0 Input
Port
Output
Port
1
NDR/
B
Input
R/W Output
<P74C>
<P74F>
0 1
0 Input
Port
Output
Port
1
Reserved EA25Output