Toshiba H1 Series - Manual (Page 230)

TMP92CZ26A
92CZ26A-227
(2) Execution of instructions on SDRAM
The CPU can execute instructions that are stored in the SDRAM. However, the following
operations cannot be performed.
a) Executing the HALT instruction
b) Changing the clock gear setting
c) Changing the settings in the SDACR, SDCMM, and SDCISR registers
These operations, if needed, must be executed by branching to other memory such as
internal RAM.
(3) Command interval adjustment function
Command execution intervals can be adjusted for each command. This function enables the
SDRAM to be accessed at optimum cycles even if the operationg frequency is changed by clock
gear.
Command intervals should be set in the SDCISR register according to the operating
frequency of the TMP92CZ26A and the AC specifications of the SDRAM.
The SDCICR register must not be changed while the SDRAM is being accessed.
The timing waveforms for various cases are shown below.
(a) Mode Register Set command
(b) Auto Refresh command
(c) Self Refresh Exit
SDCLK
COMMAND Next
Command
NOP MRS NOP NOP
TMRD
*TMRD=2CLK (SDCISR<STMRD>=”1”)
SDCLK
COMMAND NOP NOP XXX NOP
TRC
*TRC=5CLK (SDCISR<STRC2:0>= “100”)
NOP NOP Next
Command
SDCKE
Exit Self Refresh
SDCLK
COMMAND NOP NOP NOP
TRC
*TRC=5CLK (SDCISR<STRC2:0>=”100”)
NOP NOP AUTO
REFRESH
Next
Command